What is SDRAM (synchronous dynamic random-access memory)? If you want to know, then you should read this post carefully. In this post, MiniTool introduces its definition, history, generations as well as failed successors.
Introduction to SDRAM
What is SDRAM? It is short for synchronous dynamic random-access memory and it is any dynamic random access memory (DRAM) in which the operation of the external pin interface is coordinated by an externally provided clock signal.
SDRAM possesses a synchronous interface through which the change of the control input can be recognized after the rising edge of its clock input. In the SDRAM series standardized by JEDEC, the clock signal controls the stepping of the internal finite state machine in response to incoming commands.
These commands can be pipelined to improve performance and complete the previously started operations while receiving new commands. The memory is divided into several equal-sized but independent sections (called banks) so that the device can operate according to the memory access commands in each bank at the same time, and accelerate the access speed in an interleaved fashion.
Compared with asynchronous DRAM, this makes SDRAM have higher concurrency and higher data transfer rates.
History of SDRAM
In 1992, Samsung released the first commercial SDRAM – KM48SL2000 memory chip with a capacity of 16 Mb. It was manufactured by Samsung Electronics using a CMOS (complementary metal-oxide-semiconductor) fabrication process and was mass-produced in 1993.
By 2000, SDRAM had replaced almost all other types of DRAM in modern computers due to its higher performance.
SDRAM latency is not inherently lower (faster) than asynchronous DRAM. In fact, due to additional logic, early SDRAM was slower than burst EDO DRAM in the same period. The advantage of SDRAM internal buffering comes from its ability to interleave operations to multiple memory banks, thereby increasing the effective bandwidth.
Today, almost all SDRAM manufacturing meets the standards established by the electronics industry association – JEDEC, which uses open standards to promote the interoperability of electronic components.
SDRAM also provides registered varieties for systems that require greater scalability, such as servers and workstations. What’s more, now the world’s largest SDRAM manufacturers include Samsung Electronics, Panasonic, Micron Technology, and Hynix.
Generations of SDRAM
The first generation of SDRAM is DDR SDRAM, which was used to make more bandwidth available to users. This uses the same command, which is accepted once per cycle, but reads or writes two data words per clock cycle. The DDR interface accomplishes this by reading and writing data on the rising and falling edges of the clock signal.
DDR2 SDRAM is pretty similar to DDR SDRAM, but the minimum read or write unit is doubled again to reach four consecutive words. The bus protocol was also simplified to achieve higher performance. (In particular, the “burst termination” command is removed.) This allows the bus rate of SDRAM to be doubled without increasing the clock rate of internal RAM operations.
DDR3 SDRAM continues this trend, doubling the minimum read or write unit to eight consecutive words. This allows the bandwidth and external bus rate to be doubled again without having to change the clock rate for internal operations, only the width. To maintain 800-1600 M transfers/s (both edges of the 400-800 MHz clock), the internal RAM array must perform 100-200 M fetches per second.
DDR4 SDRAM does not double the internal prefetch width again but uses the same 8n prefetch as DDR3. DDR4 chip operating voltage is 1.2V or lower.
Although DDR5 has not yet been released, its goal is to double the bandwidth of DDR4 and reduce power consumption.
Failed Successors of SDRAM
Rambus DRAM (RDRAM)
RDRAM was a proprietary technology that competed with DDR. Its relatively high price and disappointing performance (due to high latencies and narrow 16-bit data channels as opposed to DDR’s 64-bit channels) made it lose the competition for SDR DRAM.
Synchronous-link DRAM (SLDRAM)
SLDRAM is different from standard SDRAM in that the clock was generated by the data source (SLDRAM chip in the case of a read operation) and transmitted in the same direction as the data, thereby greatly reducing data skew. To avoid the need to pause when the source of DCLK changes, each command specified the DCLK pair it would use.
Virtual Channel Memory (VCM) SDRAM
VCM was a proprietary type of SDRAM designed by NEC, but it was released as an open standard and did not charge a license fee. It is pin-compatible with standard SDRAM, but the commands are different.
This technology was a potential competitor of RDRAM because VCM was not as expensive as RDRAM. The Virtual Channel Memory (VCM) module is mechanically and electrically compatible with standard SDRAM, so the support of both depends only on the function of the memory controller.