Introduction to GDDR5 SDRAM – Overview and Commercialization [MiniTool Wiki]
There are different versions of synchronous dynamic random-access memory such as DDR3 RAM and DDR4 RAM. This post is mainly introducing GDDR5 RAM, and if you want to know other types of RAM, then it is recommended to visit the MiniTool website.
What Is GDDR5?
First of all, what is GDDR5 SDRAM? It is short for graphics double data rate type five synchronous dynamic random-access memory, which is a modern type of synchronous graphics random-access memory (SGRAM) with a high bandwidth interface designed for graphics cards, game consoles, and high-performance computing. It is a type of GDDR SDRAM.
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Overview of GDDR5
Similar to its predecessor - GDDR4, GDDR5 is based on DDR3 SDRAM memory, and it has double the data lines compared to DDR2 SDRAM. GDDR5 also adopts 8-bit wide prefetch buffers like GDDR4 and DDR3 SDRAM.
GDDR5 SGRAM meets the standards proposed by JEDEC in the GDDR5 specification. SGRAM is single-ported. However, it can open two memory pages at once, thus simulating the dual-port characteristics of other VRAM technologies.
It uses an 8N-prefetch architecture and DDR interface for high-performance operation, and it can be configured to operate in ×32 mode or ×16 (clamshell) mode which is detected during device initialization.
The GDDR5 interface transfers two 32-bit wide data words to/from the I/O pins every write clock (WCK) cycle. Corresponding to 8N prefetch, a single write or read access includes two CK clock cycles of 256-bit data transfer at the internal memory core and eight corresponding 32-bit wide one-half WCK clock cycle data transfers at the I/O pins.
GDDR5 works with two different clock types. The differential command clock (CK) is used as a reference for address and command input, and the forwarded differential write clock (WCK) is used as a reference for data reading and writes.
WCK’s operating frequency is twice the frequency of the CK. More precisely, GDDR5 SGRAM uses a total of three clocks: two write clocks related to two bytes (WCK01 and WCK23) and a single command clock (CK).
Taking GDDR5 with a data rate of 5 Gbit/s per pin as an example, the operating frequency of this CK is 1.25 GHz, and both WCK clocks are 2.5 GHz. During the initialization and training sequence, CK and WCK are phase aligned. This alignment allows read and write access with minimal delay.
A single 32-bit GDDR5 chip has approximately 67 signal pins, and the rest are power and grounds in a 170 BGA package.
In January 2016, JEDEC standardized GDDR5X SGRAM. The goal of GDDR5X is to achieve a transmission rate of 10 to 14 Gbit/s per pin, which is twice that of GDDR5. Essentially, it offers the memory controller with the option to use double data rate mode with 8N prefetch or quad data rate mode with 16N prefetch. While GDDR5 only has a double data rate mode with 8N prefetch.
GDDR5X also uses 190 pins per chip (190 BGA). In contrast, the standard GDDR5 has 170 pins per chip (170 BGA).
Commercialization of GDDR5
- In 2007, Hynix Semiconductor released the industry’s first 60 nm class "1 Gb" (10243 bit) GDDR5 memory.
- On May 10, 2008, Qimonda announced mass production of 512 Mb GDDR5 components with rated rates of 3.6 Gbit/s (900 MHz), 4.0 Gbit/s (1 GHz) and 4.5 Gbit/s (1.125 GHz).
- On June 25, 2008, AMD became the first company to release products using GDDR5 memory through its Radeon HD 4870 video card.
- In 2010, Hynix 40 nm class "2 Gb" (2 × 10243 bit) GDDR5 was released. It runs at an effective clock speed of 7 GHz and has a processing speed of up to 28 GB/s.
- In the third quarter of 2013, "4 Gb" (4 × 10243 bit) GDDR5 components were put into use. Originally released by Hynix, Micron Technology quickly followed up, and its implementation was released in 2014.
- In February 2014, with the acquisition of Elpida, Micron Technology added 2 Gb and 4 Gb GDDR5 products to the company's graphics memory solution portfolio.
- As of January 15, 2015, Samsung announced in a press release that it has begun mass production of "8 Gb" (8 × 10243 bit) GDDR5 memory chips based on a 20 nm fabrication process.