Though the speed of SSD is usually faster than that of the traditional hard disk drives, the capacity is actually not as large as that of HDDs. Thus, many people try every means to improve the capacity of an SSD. Besides, there are also people who still want to make the SSD faster. That’s what the bridge chip is used for.
Toshiba Bridge Chip Is Announced
At the end of last month, the world leader of memory solutions – Toshiba Corporation – has announced the release of bridge chip, which is developed to improve both the capacity and speed of SSDs. Two of the most obvious advantages of the Toshiba bridge chip are:
- It has a small occupied area.
- The power consumption of the new bridge chip is low.
Compared to the conventional methods which have no bridge chips, adopting the Toshiba memory chip help to connect more flash memory chips with fewer high-speed signal lines. This was made known to the public at the International Solid-State Circuits Conference 2019 (ISSCC 2019), held in San Francisco on February 20, 2019.
A New Way to Connect Controller & Flash Chips of SSDs
In general, multiple flash memory chips will be connected to a controller which is capable of managing the operations of SSDs (Solid-State Drive).
Difficulty:
As a matter of fact, the number of chips that can be connected to a controller interface is limited. Why? That is because the operating speed will be affected a lot with the increasing number of flash memory chips connecting to the controller.
In addition, you should be clear that it is necessary to add the number of interfaces so as to increase the capacity. The result of doing this:
- There will be more high-speed signal lines that are connected to the controller.
- It would be much more difficult to configure the wiring on the board of SSD.
Solution:
The new bridge chip (which is able to connect the controller and flash memory chips) was developed by Toshiba as a solution to solve the problem. Three novel techniques are included:
- A serial communication, in which the PAM 4 is used
- A daisy chains connection, in which the controller and bridge chips are included in a ring shape
- A jitter improvement technique, which is adopted for taking away a PLL circuit from the bridge chips
These techniques are working together to reduce the overhead of the bridge chips. In addition, you are allowed to operate a large number of flash memory chips at high speed by taking advantage of only a few high-speed signal lines. In this way, both the speed and capacity of SSDs will be improved a lot.
How It Works
By configuring the bridge chips and the controller in ring shape, you can achieve the following goals:
- Reduce the chip area of the Toshiba memory chip greatly.
- Reduce the number of transceivers (that are needed in the bridge chip) from two pairs to only one pair.
By adopting PAM 4 serial communication between the daisy-chained bridge chips and the controller, you can achieve the following goals:
- Relax the performance that is needed.
- Slow down the operating speed in the circuits of bridge chip.
By applying the characteristics of PAM 4 to the new CDR, you can achieve the following goals:
- Improve the jitter characteristics.
- Cancel the requirements for a PLL circuit in the bridge chip.
- Shrink the chip area.
- Reduce the power consumption.
Verdict
The 28nm CMOS process is used in the prototype bridge chips. Four bridge chips and a controller are configured in a ring-shape daisy chain in order to evaluate the results. Now, we know that PAM 4 communication can gain a satisfactory performance if all of the bridge chips and the controller at 25.6 Gbps; in addition, a BER which is less than 10-12 can be gained.
In the future, the Toshiba Corporation will continue to develop the high-speed and large-capacity storage. The performance of the Toshiba bridge chip will be enhanced further and the area & power consumption of the chip will be reduced.
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